Technical Field
The present invention relates to a bus control device, an image processing apparatus, and a bus control method, and more specifically to a bus control device, an image processing apparatus, and a bus control method each of which is capable of arbitrating a bus obtaining request.
Description of the Related Art
The recent data processing apparatuses, such as image processing apparatuses including, for example, multifunctional peripherals, printers, copiers, scanners, and facsimiles, may be provided with a plurality of units such as a scanner unit, printer unit, and controller provided with an image memory. These units are connected through a general-purpose bus that functions as a common interface. Providing the general-purpose bus suppresses the addition of a circuit that may not be useful or the increase in number of control software components, which may be caused due to extension of units, while at the same time improving scalability of the system.
For the integrated circuit (IC) such as the Application Specific Integrated Circuit (ASIC) or the System on Chip (SoC) incorporating a sub CPU, each module is connected to a memory via an internal bus such that each module accesses the bus according to a bus protocol. More specifically, the module is provided with a bus master such as a direct memory access controller (DMAC). The bus master outputs a bus obtaining request to a bus arbiter, and when permitted, obtains an access right to the memory via a slave. In such case, the bus arbiter, which is capable of assigning a priority level, defines a priority level for each bus master. For example, assuming that the bus arbiter receives a bus obtaining request from a high-priority bus master one cycle after the time at which the request is received from the low-priority bus master, the bus arbiter assigns the low-priority bus master with a memory access right such that the bus will be used by the low-priority bus master for a predetermined time period. This may not be desirable in some cases. For example, the image processing apparatus includes devices that may require isochronous transfer (real-time capability) such as scanners or printers, and devices that may not require isochronous transfer. In such case, it is desirable to assign a bus master access right to the devices requiring isochronous transfer with higher priority.
Japanese Patent Application Publication No. JP-2002-269032-A proposes a bus arbiter. When there is a bus acquirement request from a first bus master, which is generated with the occurrence of a specified event in a device provided with the bus arbiter, the frequency in assigning a bus use right is restricted more than a regular case where the specified event is not generated, with respect to the bus acquirement request from the bus master other than the first bus master. More specifically, the bus acquirement request from the other bus master is masked for a predetermined time period to prohibit the access right from being assigned to the other bus master, thus securing a bus range for use by the first bus master. In order to assign a bus access right to a specific bus master with higher priority through masking the bus acquirement request for the other bus master, a mask time measurement unit such as a counter to restrict the frequency in assigning the bus access right is provided for each of a plurality of masks. Since the mask time measurement unit is provided for each mask, with the increase in number of bus masters due to the demands for larger ASIC or SoC systems, the number of mask time measurement units for controlling the bus access right increases. This may result in larger circuit sizes, more complicated circuit designs, or higher costs.